diff -urN /usr/src/linux-2.6.25/include/asm-arm/arch-at91/at91_wdt.h ./at91_wdt.h
--- /usr/src/linux-2.6.25/include/asm-arm/arch-at91/at91_wdt.h  2008-06-14 13:34:32.000000000 -0400
+++ ./at91_wdt.h        2008-06-14 13:21:47.000000000 -0400
@@ -1,9 +1,6 @@
 /*
  * include/asm-arm/arch-at91/at91_wdt.h
  *
- * Copyright (C) 2007 Andrew Victor
- * Copyright (C) 2007 Atmel Corporation.
- *
  * Watchdog Timer (WDT) - System peripherals regsters.
  * Based on AT91SAM9261 datasheet revision D.
  *
@@ -18,7 +15,7 @@

 #define AT91_WDT_CR            (AT91_WDT + 0x00)       /* Watchdog Control Register */
 #define                AT91_WDT_WDRSTT         (1    << 0)             /* Restart */
-#define                AT91_WDT_KEY            (0xa5 << 24)            /* KEY Password */
+#define                AT91_WDT_KEY            (0xA5 << 24)            /* KEY Password */

 #define AT91_WDT_MR            (AT91_WDT + 0x04)       /* Watchdog Mode Register */
 #define                AT91_WDT_WDV            (0xfff << 0)            /* Counter Value */
@@ -34,4 +31,20 @@
 #define                AT91_WDT_WDUNF          (1 << 0)                /* Watchdog Underflow */
 #define                AT91_WDT_WDERR          (1 << 1)                /* Watchdog Error */

-#endif
+#define AT91_RSTC_MR           (AT91_RSTC + 0x08)
+#define     AT91_RSTC_KEY           (0xA5 << 24)
+#define     AT91_RSTC_URSTEN         (0x01 <<  0) // (RSTC) User Reset Enable
+#define     AT91_RSTC_URSTIEN        (0x01 <<  4) // (RSTC) User Reset Interrupt Enable
+
+/*
+ * The value for the ERSTL bits isn't a "guess"
+ * The range for ERSTL is 60us to 2 sec, and this dictates the external reset length
+ * 2 sec is a violation of the Atmel boot program algorithm
+ * where RomBOOT first tries to detect SPI Dataflash and the timeout
+ * for this detection is "< 1 sec", so our reset time in the case of a
+ * DataFlash boot needs to be < "< 1 sec"
+ * A setting of 8 is 2^(8+1) (2 raised to the power of 8+1) slow clock cycles
+ * 2^(8+1)=512 msec of of external reset
+ */
+
+#define     AT91_RSTC_ERSTL          (0x8  <<  8) // (ERSTL) External Reset Length
diff -urN sam9_watchdog.c orig_sam9_watchdog.c
--- sam9_watchdog.c     2008-06-14 12:39:02.000000000 -0400
+++ orig_sam9_watchdog.c        2008-06-14 10:56:07.000000000 -0400
@@ -92,10 +92,8 @@

        /* Program the Watchdog */
        reg = AT91_WDT_WDRSTEN                  /* causes watchdog reset */
-#if defined(CONFIG_MTD_DATAFLASH)
-               /*| AT91_WDT_WDRPROC  */        /* causes processor reset */
-               /*| AT91_WDT_WDDBGHLT */        /* disabled in debug mode */
-#endif
+               | AT91_WDT_WDRPROC              /* causes processor reset */
+               | AT91_WDT_WDDBGHLT             /* disabled in debug mode */
                | AT91_WDT_WDD                  /* restart at any time */
                | (((wdt_timeout * 256) - 1) & AT91_WDT_WDV);
        at91_sys_write(AT91_WDT_MR, reg);
@@ -107,14 +105,6 @@
                return -EIO;
        }

-#if defined(CONFIG_MTD_DATAFLASH)
-       reg = 0;
-    reg = AT91_RSTC_KEY
-                 | AT91_RSTC_ERSTL             /* set externel reset as short as possible */
-                 | AT91_RSTC_URSTEN;   /* enable user reset                                       */
-    at91_sys_write(AT91_RSTC_MR, reg);
-#endif
-
        at91_wdt_reload();

        printk(KERN_INFO "AT91SAM9 Watchdog enabled (%d seconds, nowayout)\n",